1. Field of the Invention
The invention relates to a dummy filling methodology that can improve planarization of chip surface topography.
2. Description of the Related Art
A typical wafer for an integrated circuit (IC) includes multiple layers formed on a substrate. These layers, each layer having a predetermined pattern thereon, can result in an uneven topography on the wafer surface. An uneven topography on one layer can have adverse effects on one or more subsequent layers.
For example, FIG. 1A illustrates a cross-section of an etched aluminum layer 100 on a wafer, wherein etched aluminum layer 100 includes two features 101 and 102. Both features 101 and 102 extend above a level 103 as protrusions. If another layer 104 is formed on etched aluminum layer 100, as shown in FIG. 1B, layer 104 can also have an uneven surface due to the uneven topography of layer 100. The uneven surface of layer 104 can undesirably complicate lithographic processing on this layer because of light reflection or inadequate coverage over the “steps” in layer 100.
A common technique used to counter the effects of an uneven topography is planarization. The goal of planarization is to ensure that subsequent lithographic results are independent from or, more realistically, much less dependent on the underlying wafer topography from previous layers. Planarization is especially important for layers requiring critical dimension control. Specifically, an uneven topography could pose significant depth of focus problems, thereby rendering CD control across the wafer virtually impossible.
However, planarization itself can cause problems on the wafer. For example, in one known planarization process shown in FIG. 1C, a thick spin-on-glass (SOG) layer 105 can be formed on etched aluminum layer 100. After formation, SOG layer 105 is baked, thereby leaving substantially planarized silicon dioxide. The resulting surface, although significantly more even than layer 104, still retains irregularities that can influence a subsequent lithographic process. For this reason, a chemical-mechanical polish (CMP) can be used to polish SOG layer 105.
In a CMP process, a device mechanically polishes the surface of the wafer. Unfortunately, because of the underlying features in layer 100, such as features 101 and 102, the polishing of layer 105 can result in an uneven force being applied to certain areas of the surface of the wafer. In turn, this uneven force can cause some areas to polish faster than other areas, thereby resulting in an uneven polished surface. FIG. 1D illustrates a recessed area 106 that could result from a CMP of layer 105.
To reduce systematic topography variations, electrically inactive features, called “dummy” features, have been placed on regions of the wafer to provide mechanical support during a CMP. For example, FIG. 2 illustrates a top-level view of a layer 200 including two main features 201 and 202 and dummy features 203 and 204. The process of introducing these dummy features is often referred to as “dummy filling”.
The primary objective of conventional dummy filling is to reduce the density difference between the different regions in the layout. Notably, when aluminum was used as the interconnect material, the primary source of chip topography variations was due to non-uniformities after the inter-layer dielectric (ILD) CMP process. Such topography variations after ILD CMP are primarily due to the inherent density differences between the different regions of the layout as oxide deposition was conformal and the final thickness after CMP depended on the underlying density of the location. Hence, for fabrication using aluminum, dummy filling based solely on density was effective in reducing topography variations.
The advent of copper interconnect in sub-130 nm integrated circuits has introduced additional complexity in forming a planar topography. Specifically, during the copper metallization process, trenches for wires and holes for vias are etched in a dielectric material. After etching, electroplating (ECP) is performed to fill up the trenches/holes with copper and then CMP is performed to remove excess copper from the dielectric surface, thereby leaving copper in the trenches/holes as interconnect wires/vias.
FIG. 3 illustrates a cross section of a set of topographies 300 after ECP based on various underlying trench patterns. Notably, topographies 300 can vary dramatically based on the underlying line/space pattern. Exemplary patterns include fine line/fine space pattern 301, large line/large space pattern 302, fine line/large space pattern 303, and large line/fine space pattern 304.
Variations in post-ECP topography are typically propagated through CMP, thereby adversely affecting final chip topography. Specifically, a barrier metal layer 305 (e.g. Ta2N3) is typically formed between the underlying etched oxide layer 306 and the copper layer 307. During CMP, barrier metal layer 305 is polished more slowly than copper layer 307. Notably, the uppermost horizontal sections of barrier metal layer 305 must be removed during CMP to prevent shorting. Therefore, some of the copper lines may have sole loss of planarity to ensure complete barrier metal removal. As a result, a topography variation after ECP can be propagated to the chip topography after CMP, even though the CMP reduces the ECP non-uniformity.
In general, a variety of layout parameters besides density can affect the topography during copper processing. For example, referring to topologies 300 of FIG. 3, fine line/fine space pattern 301 and large line/large space pattern 302 have the same density. Therefore, the resulting topologies of these areas should be the same. However, as shown in FIG. 3, these two areas actually end up with very different topographies.
Variations in final chip topography can cause functional and parametric yield problems, e.g. focus issues in lithography as well as sheet resistance and parasitic capacitance variations in the timing. To further complicate matters, the depth of focus (DOF) budget and interconnect thickness values are continually shrinking with each technology node. Therefore, reducing the systematic topography variations during the fabrication process is of paramount importance.
Unfortunately, it is no longer sufficient to reduce only the density differences between the different regions in the layout during dummy filling. In fact, in some cases, density-based dummy filling could even have a detrimental effect on the final chip topography. Therefore, a need arises for a dummy filling methodology that takes ECP into account.